This invention relates to the field of fabricating integrated circuits. More particularly, this invention relates to the design, layout, and use of reticles in photolithographic manufacturing of integrated circuits.
In a photolithographic manufacturing process for integrated circuits, it is common to use reticles upon which patterns are formed. The patterns are also called xe2x80x9clayer patternsxe2x80x9d herein because the patterns are imaged onto an integrated circuit substrate that is coated with a light sensitive material, to ultimately pattern a layer of an integrated circuit. Typically, multiple reticles are required to produce a desired integrated circuit. A significant amount of money is generally devoted to producing the reticles needed for fabricating the integrated circuits. For example, a single integrated circuit may require twenty to thirty reticles, at a cost of several thousand dollars each. Thus, the time and expense of producing reticles is of particular concern. This is especially of concern in low volume integrated circuit fabrication, such as prototyping or other design verification.
In the present invention, the time and expense for producing reticles is minimized by designing the reticle to have multiple different layer patterns formed thereon for producing multiple different layers of the same or different integrated circuits.
In accordance with an embodiment of the present invention, an apparatus is provided for producing integrated circuits that includes a reticle with a number of layer patterns disposed on the reticle. At least some of the layer patterns on the reticle are different from others of the layer patterns and the layer patterns are selected from a group of same circuit layer patterns and different circuit layer patterns. A same circuit layer pattern corresponds to different layers of one design of an integrated circuit and different circuit layer patterns correspond to different layer patterns from different designs of integrated circuits.
A light source provides and directs light onto individual layer patterns on the reticle, and an integrated circuit substrate is disposed to receive light from the reticle. An image is formed on the integrated circuit substrate, and the image corresponds to one of the layer patterns on the reticle. A scanner moves the integrated circuit substrate relative to the reticle, and a controller associated with the scanner controls the relative positioning of the integrated circuit substrate. The controller causes selected images of the layer patterns to be projected on or disposed on selected areas of the integrated circuit substrate. Thus, the layer patterns on the reticle are imaged onto the substrate as part of a photolithographic process that produces one or more desired integrated circuits.
In this manner, several different mask layers for a single integrated circuit design, such as a prototype design, are placed on a single reticle, rather than on multiple reticles. Thus, fewer reticles are required to fabricate the integrated circuit, and less expense is incurred in producing the mask set. Alternately, the different mask layers on a single reticle are used for the various layers of different integrated circuit designs, rather than for the layers of a single integrated circuit design. This also reduces the number of reticles that are needed to fabricate the different integrated circuit designs. Although this type of reticle is preferably used for prototype fabrication, or very small run production, it could also be used in full scale production of integrated circuits.
In accordance with a method embodiment of the present invention, a plurality of layer patterns are formed on a reticle. The layer patterns are selected from the group of same circuit layer patterns and different circuit layer patters, where the same circuit layer patterns correspond to different layers of one design of an integrated circuit and where the different circuit layer patterns correspond to different layer patterns from different designs of integrated circuits.
In one embodiment, the reticle is used in a photolithographic process to project multiple different images on the same area of an integrated circuit substrate to form multiple layers of one integrated circuit.
In an alternate embodiment of the method, the reticle may also be used to project multiple different images on different areas of one or more integrated circuits to form layers of different design on one or more integrated circuit substrates. Alternately, an embodiment could use the reticle to do both of the above methods in the same process. That is, the reticle would be used to project multiple different images on the same area of an integrated circuit to form multiple layers of one integrated circuit design and the reticle would be used to project multiple different images on different areas of one or more integrated circuit substrates to form layers of different integrated circuit designs.
In accordance with a more detailed embodiment of the present invention, a method produces an integrated circuit by providing an integrated circuit substrate and forming a light sensitive layer on the substrate. The light sensitive layer reacts when exposed to light. A reticle is also provided and a plurality of layer patterns are formed on the reticle. The layer patterns are selected from the group of same circuit layer patterns and different circuit layer patterns where the same circuit layer patterns correspond to different layers of one design and where the different circuit layer patterns correspond to different layer patterns from different designs.
Light is directed onto one pattern of the reticle and the light sensitive layer is exposed to light from the one pattern so that a light image of the one pattern is formed on the light sensitive layer. The light image on the light sensitive layer forms a reacted region in the form of the light image of the one pattern. A portion of the light sensitive layer is removed from the integrated circuit to form a desired pattern in the light sensitive layer corresponding to the reacted region. The substrate is then processed to form a desired feature in or on the substrate corresponding in part to the desired pattern in the light sensitive layer.
A new layer of integrated circuit material is formed over the desired features and a new light sensitive layer is formed over the new layer of integrated circuit material. Light is again directed onto the reticle, but this time onto a different pattern of the reticle. Light from the different pattern is exposed onto the new light sensitive layer on the integrated circuit substrate to form a light image of the different pattern. The light sensitive layer reacts to the light image to form a new reacted region in the light sensitive layer in the form of the light image of the different pattern. Again, a portion of the light sensitive layer is removed from the integrated circuit substrate to form a new desired pattern in the light sensitive layer corresponding to the new reacted region.
The substrate is then processed to form new desired features on the substrate corresponding in part to the new desired pattern in the light sensitive layer. Thereafter, the remaining portion of the light sensitive layer is removed and the steps of forming new layers of integrated circuit material and a new light sensitive layer are repeated followed by a repetition of the directing, exposing, removing, processing and the second removing step. These series of steps are repeated until a desired integrated circuit is constructed.
In accordance with yet another embodiment of the present invention, a reticle is produced for making layers for one or more designs of integrated circuits. For a particular integrated circuit scanner, a maximum field size is determined and then within that maximum field size, a field size for each sub field in a plurality of x by y arrays of sub fields is determined. In making this determination, the size of the borders around and between the sub fields as required by the particular scanner is considered. The size of sub fields for different x by y arrays is determined where x and y define the number of rows and columns in the array and where x and y vary within a predetermined range.
The maximum size of a selected layer pattern in a particular integrated circuit design is determined and then an array is selected to have sub fields with dimensions sufficient to contain the selected layer pattern. At least a portion of the selected array is formed on the reticle to form at least one sub field on the reticle. Then, the selected layer pattern is formed in the sub field of the reticle. If additional layer patterns are needed, the above steps of determining a maximum field size, determining maximum sub field sizes, selecting, forming a portion of the array and forming a selected layer pattern are repeated until the reticle is full.
In the above method, sub fields from only one array may be formed on the reticle, or sub fields from different arrays may be formed on the reticle. Preferably, the centers of the sub field and the centers of each layer pattern are aligned and the scanner is programmed to position the integrated circuit substrate relative to the layer patterns based on the positions of the centers of the sub fields.